Research Assistant in Fault-Tolerant Systems Design and Testing

Texts/Reference Books

Robust SRAM Designs and Analysis, Springer, with J. Singh and S P Mohanty, ISBN 978-1-4614-0817-8, 2012.
Eco-friendly Computing and Communication Systems. . ISBN 978-3-642-32111-5. August 2012 (with J. Mathew, Patra P., Dhiraj Pradhan, Kuttyamma).
Memory management techniques for embedded VLSI systems, CRC Press, with Balasa, Florin, ISBN 978-1-1-4398-1400-0, 2012
Practical Design Verification, Cambridge University Press, with Ian Harris, ISBN 978-0-521-85972-1, 2009.
Fault-Tolerant Computer Systems Design; Prentice Hall,1996 ; Second Printing; 2003; adopted as text worldwide.
On-Line Testing for VLSI, Springer, co-edited with M. Nicolaidis and Y. Zorian, ISBN 978-0-7923-8132-7, 1998.
IC Manufacturability: The Art of Process and Design Integration, (with J. de Gyvez), IEEE Press, 1999.
Fault-Tolerant Systems Design, (Editor and Co-Author), Prentice-Hall, Inc.; 1996.
Fault-Tolerant Computing: Theory and Techniques (Editor, Co-Author), vols. I & II; Prentice-Hall, Inc; 1986.

Book Chapters

Computer-Aided Design for Energy Optimization in the memory Architecture of Embedded Systems, (with Florin Balasa), in Energy-Aware Memory Management for Embedded Multimedia Systems, CRC Press, 2012.
Word Level Representation for Verification and Synthesis (with M. Ciesielski), in Practical Design Verification, Cambridge University Press, 2009.
Fault-Tolerant Computing, (with B. Joshi and J. Stiffler) in Wiley Encyclopedia of Computer Science and Engineering, Wiley Press, 2009.
Communication Structures in Fault-Tolerant Distributed Systems (with F.J. Meyer), in Hardware and Software Fault-Tolerance in Parallel Computing Systems, Simon & Schuster International Group; Chichester, England, D. Avresky, Editor; 1992
New Roll-Forward Checkpointing Schemes for Modular Redundant Systems, (with N. Vaidya), in Hardware and Software Fault-Tolerance in Parallel Computing Systems, Simon & Schuster International Group; Chichester, England, D. Avresky, Editor; 1992.
Computer Reliability, (with J. Stiffler) in Encyclopedia of Microcomputers, vol. 4, Marcel Dekker, Inc; New York; 1990.
An Efficient Coordinated Checkpointing Scheme for Multicomputers, (with D. Das Sharma); in Fault-Tolerant Parallel and Distributed Systems, IEEE Computer Society Press; 1995.
Roll-Forward Checkpointing Schemes, (with D. Das Sharma and N. Vaidya), in Hardware and Software Architectures for Fault Tolerance: Perspectives and Towards a Synthesis; Springer Verlag, 1994.(This scheme has been adapted in a HP Server).

Journals

1. Attack Tolerant Cryptographic Hardware Design by Combining Error Correction and Uniform Switching Activity. Elsevier Journal of Electrical and Computer Engineering, January 2013(with J. Mathew, S.P.Mohanty).

2. Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integration, the VLSI Journal, 45( ), pp. 33–45. June 2012 (S P Mohanty, J Singh, E. Kougianos)

3. "Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits" Journal of JOLPE, Vol. 8, No. 3, June 2012. (with Luo Sun, Jimson Mathew, Saraju P. Mohanty).

4. Fault Tolerant High Performance Galois Field Arithmetic Processor. Lecture Notes in Computer Science, . August 2012 (with Narayanan, V.K, Shafik, R.A, J. Mathew)

5. VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases . Lecture note in Computer Science (LNCS) , Springer. ISSN 0302-9743, pp. 258–269. July 2012 (H Rahaman, J. Mathew, A. M. Jabir)

6. "Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks, Journal of Circuits and Systems" Journal of Embedded Signal Processing Circuits and Systems for Cognitive Radio-based Wireless Communication Devices (Springer) 2011, (with J. Mathew, K. Maharatna).

7. "A Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization" Journal of JOLPE Special Issue, Vol. 7, No. 4, October 2011. (with S. Banerjee, J. Mathew, S. Mohanty)

8. "Fault Tolerant Single Error Correction Encoders" Journal of Electronic Testing: Theory and Applications, Vol. 27, No. 2, April 2011. (with P. Reviriego, C. Argyrides, J. A. Maestro)

9. "Improving Memory Reliability against Soft Errors Using Block Parity" IEEE Transactions on Nuclear Sciences, Vol. 58, No. 3, June 2011. (with P. Reviriego, C. Argyrides, J. A. Maestro)

10. "Reliability Analysis of H-Tree RAM Memories Implemented with BICS and Parity Codes for Multiple-Bit Upset Correction" IEEE Transactions on Reliability, (with C. Argyrides, F. Vargas)

11. "A Routing-Aware ILS Design Technique", IEEE Transactions on Very Large Scale Integration Systems 2011(to appear). (with S. Banerjee, J. Mathew).

12. "Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph", IEEE Trans. VLSI Syst. 01/2011; 19:1469-1480, (with Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew).

13. "DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM". Journal of Low Power Electronics, 6(3). pp. 390 - 400, October 2010 (with S. Mohanty).

14. ULS: A Dual-Vth/High-K Nano-CMOS Universal Level Shifter for System-Level Power Management. ACM Journal of Emerging Technologies in Computing (JETC), 6(2), pp. 8:1-8–26. June 2010 (with S. Mohanty).

15. "A Novel Fault Diagnosis Technique in Wireless Sensor Networks". The International Journal On Advances in Networks and Services, pp. 230 - 240, March 2010 (with Anas Abu Taleb, J. Mathew)

16. "Test Generation in Systolic Architecture for Multiplication over GF(2^m)" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 9.pp. 1366 - 1371, Sept. 2010. (with H. Rahman, J. Mathew)

17. "Matrix-Based Codes for Adjacent Error Correction" IEEE Transactions on Nuclear Sciences, Vol 57, no.4, pages 2106 - 2111, Aug 2010. (with C. Argyrides, P. Reviriego, J. A. Maestro)

18. Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability, IET Computers & Digital Techniques" Volume : 4 , Issue:5, pp- 428- 427, July, 2010. (with H. Rahman, J. Mathew).

19. , "Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 99.pp. 1-12, June 2010. (with M. Hosseinabady,J. Mathew)

20. Secure Testable S-box Architecture for Cryptographic Hardware Implementation. The Computer Journal, (2010) 53 (5): 581-591, April 2010. (with H. Rahaman, J. Mathew).

21. A Galois Field Based Logic Synthesis Approach with Testability. IET Computers & Digital Techniques, pp. 263-273, July 2010, (with J. Mathew, A. M. Jabir, H. Rahaman).

22. On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED, Journal of Electronics, pp. 1161 – 1173, 2009 (with J Mathew, A Jabir, H. Rahaman, C. Argyrides)

23. Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),. International Journal of Electronic Science and Technology, pp. 336-342, July 2009. (with A.K Singh, A Bera, H. Rahaman, J. Mathew)

24. Single Error Correctable Bit Parallel Multipliers Over GF(2^m). IET Computers & Digital Techniques, pp. 281-288, May 2009 (with J. Mathew, A. M. Jabir, H. Rahaman)

25. Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1689-1692 (2008) (with Jayawant Kakade, Dimitrios Kagaris).

26. "Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). WSEAS:Transactions on Circuit and Systems, pp. 422 - 430. (with H. Rahaman, Jimson Mathew, B. K. Sikdar)

27. "Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2^m)" IEEE Transactions on Computers, pp. 1289-1294, 2008. (with H. Rahaman, J. Mathew).

28. "On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography", Lecture Notes in Computer Science (LNCS), pp. 96-104, 2008. (with D. Maslov, J. Mathew and Donny Cheung).

29. "C-Testable Bit Parallel Multipliers Over GF(2^m)". ACM Transactions on Design Automation of Electronic Systems (TODAES), January 2008 (with H. Rahaman, J Mathew, A. M. Jabir).

30. "A Defect Tolerance Scheme for Nanotechnology Circuits" IEEE Trans. On Circuits and Sytems I, pp. 2402 – 2409, December 2007. (with Ahmad Al-Yamani, S. Ramsundar).

31. Gfxpress: An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). In:IEEE Transactions on Computer Aided Design, (IEEE TCAD), IEEE, pp. 698-711, November 2008 (with A. Jabir, Dhiraj Pradhan and J. Mathew).

32. "Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circui tBehavioral Synthesis" IEE Proceedings, March 2008 (with S. Mohanty).

33. "A Graph-based Unified Technique for Computing and representing Coefficients over Finite Fields", (with A. M. Jabir). Transactions on Computers, pp. 1119-1132, June 2007.

34. "EBIST: A Novel Test Generator with Built-In-Fault Detection Capability", (with C. Liu), IEEE Transactions on CAD, Vol. 24(9), pp. 1457 – 1466; Sept. 2005.

35. "NIVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT Instances", (with S. Subbarayan) In Selected Revised Papers of International Conference on Theory and Applications of Satisfiability Testing Conference, SAT-2004, pp.276-291, (Springer LNCS).

36. "LPRAM: A Novel Low-Power RAM Design with Testability", (with S. Bhattacharjee), IEEE Transactions on CAD, Vol. 23, pp. 637-651; May 2004.

37. "A GLFSR-Based Pattern Generator for Near-Perfect Fault Coverage in BIST", (with M. Chatterjee), IEEE Transactions on Computers, Vol. 52, pp. 1535-1542; Dec. 2003.

38. "VERILAT: Verification using Logic Augmentation and Transformations", IEEE Transactions on CAD; pp.1041-1051; Sept., 2000.

39. "Buffer Assignment Algorithms and Date-Driven ASCIIs" (with S. Banerjee and M. Chatterjee); IEEE Transactions on Computers: pp. 16-32; Jan., 2000.

40. "GLFSR: A Novel Method for Test Generation in BIST Environment, IEEE Transactions on CAD; pp.238-247; Feb' 99.

41. "Job Scheduling in Mesh Multicomputers", (with D. Das Sharma); IEEE Transactions on Parallel and Distributed Systems;' Vol. 9, pp. 57-70, Jan., 1998.

42. "LOT: Logic Optimization with Testability: New Transformation using Recursive Learning", IEEE Transactions on CAD; Vol. 17, no. 5, pp. 386 – 399; May, 1998.

43. "A Novel Routing Strategy for Ad-Hoc Wireless Local Area Networks", (with N. H. Vaidya, M. Chatterjee); ACM SIGCOMM Computer Communications Review; April, '97.

44. "Roll-Forward and Rollback Recovery: Performance Reliability Trade-Off" (with N. Vaidya), IEEE Transactions on Computer; Vol. 46, pp. 372 – 378; March '97.
45. "Issues in Fault Tolerant Memory Management" (with N. Bowen), IEEE Transactions on Computers; pp.868-880; Aug'96.

46. "Synthesis of Initializable Asynchronous Circuits"; IEEE Transactions on VLSI Systems; vol. 4;pp. 254-263; June, '96.

47. "A Novel Framework for Logic Verification in a Synthesis Environment" (with W. Kunz and S.M. Reddy), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; vol. 15, no. 1, pp. 20 – 32; Jan.'96.

48. "Utilization of On-Line (concurrent) Checkers During Built-In Self-Test and vice-versa" (with S. Gupta), IEEE Transactions on Computers; vol. 45, no.1, pp. 63 – 73; Jan. '96.

49. "Submesh Allocation in Mesh Multicomputers using Busy-List: A Best-Fit Approach with Complete Recognition Capability" (with D. Das Sharma), Journal of Parallel and Distributed Computing, Academic Press; vol. 36, no. 2, pp. 106 – 118; Aug.' 96.

50. "Fault Injection: A Method for Validating Computer-System Dependability" (with A. J. Clark), IEEE Computer Society; vol. 28, no. 6, pp. 47 – 56; June' 95.

51. "A Survey of Fault-Injection Experimentation for Validating Computer System De pendability" (with J. Clark), IEEE Computer Magazine; pp. 47 – 56; June' 95.

52. "Novel Scheme to Reduce Test Application Time in Circuits with Full Scan" (with Saxena and Jayashree), IEEE Transactions on Computer-Aided Design of Integrated Circuit Systems; Vol, 14, no. 12, pp. 1577 – 1586; 1995.

53. "Can Concurrent Checkers Help BIST?" (with S. Gupta), IEEE Transactions on Computers; pp.140-150, Sep. 1992.

54. "Static and Dynamic Location Management in Distributed Mobile Environments", (with P. Krishna & N. H. Vaidya); Computer Communications (Special Issue on Mobile Computing); June 94.

55. "A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithm" (with N. Bowen), IEEE Transactions on Computers; vol. 44(3), pp. 408 – 418.
56. "Degradable Byzantine Agreement" (with N. Vaidya), IEEE Transactions on Computers; vol. 44(l), pp. 146 – 149; Jan.,'95.
57. "Communication Structures in Fault-Tolerant Distributed Systems" (with F. J. Meyer NETWORKS; vol. 23, pp. 379 – 389; '93.
58. "Yield Optimization of Redundant Multimegabit RAM's Using the Center-Satellite Model" (with D. Das Sharma and F. Meyer), IEEE Transactions on VLSI Systems; pp. 200-209, Dec., '93.
59. "A Scheme to Reduce Test Application Time in Circuits with Full Scan" (with J. Saxena), IEEE Transactions on Computer-Aided Designs of Integrated Circuits and Systems; vol. 14, no. 12, pp. 1577 – 1586; Dec.,'95.
60. "Utilization of On-line (concurrent) Checkers During Built-in self-test and vice versa" (with S. Gupta), IEEE Transactions on Computers; vol. 45, no. 1, pp. 63-73, Jan. 1996.
61. "A Novel Framework for Logic Verification in a Synthesis Environment" (with W. Kunz and S. Reddy), IEEE Transactions on Computer-Aided Design, vol. 15, no. 1, pp. 20-32, Jan. 1996.
62. "The Effect of Program Behavior on Fault Observability" (with N. Bowen), IEEE Transactions on Computers; vol. 45, no. 8, pp. 868-880, Aug. 96.

63. "Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Non-Cubic Allocation" (with D. Das Sharma), IEEE Transactions on Parallel and Distributed Systems; vol. 6(10), pp. 1108 – 1123; Oct.,'95.
64. "The Hierarchical Full-Map Directory Scheme: Protocol and Performance" (with Y. C. Maa and D. Thiebault), IEEE Transactions on Computers;' pp. 43-46, March 1992.

65. "Safe System Level Diagnosis" (with N. Vaidya), IEEE Transactions on Computers; vol. 43(3), pp. 367 – 370; March.'94.
66. "Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems" (with W. Kunz), IEEE Transactions on Computer-Aided Design; pp.1143-1158; Sept.,'94.
67. "Roll Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture" (with N. Vaidya), IEEE Transactions on Computers; vol. 43(10), pp. 1163 – 1174; Oct.,'94.

68. "The Hyper-de Bruijn Networks: Scalable Versatile Architecture";(with E.Ganesan); Transactions on Parallel and Distributed Systems; vol.4, no.9, pp. 962-978; Sept.,'93.
69. "The Effect of Memory-Management Policies on System Reliability" (with N. Bowen), IEEE Transactions on Reliability; vol. 42, no. 3, pp. 375 – 383; Sept.,'93.
70. "Processor and Memory Based Checkpoint and Rollback Recovery" (with N.S. Bowen), COMPUTER; pp. 22 – 31; Feb.,'93.
71. "Recursive Learning: A Precise Implication Procedure and Its Application to Test Pattern Generation in Digital Circuits" (with W. Kunz), IEEE Transactions on Computer-Aided Design; June.'94.
72. "A Hybrid Memory Structure and Algorithms for Improved Fault Tolerance" (with N. S. Bowen), IEEE Transactions on Computers; vol. 44(3), pp. 408 – 418; March.'95.
73. "Modeling Live and Dead Lines in Cache Memory Systems" (with D. Thiebaut and A. Mendelson), IEEE Transactions on Computers; vol. 42, no. 1, pp. 1 – 14; Jan.,'93.
74. "A New Algorithm for Rank-Order Filtering and Sorting" (with Barun Kar), IEEE Transactions on ASSP; vol. 41, no. 8, pp. 2688 – 2694; Aug.,'93.
75. "Virtual Checkpoints: Architecture and Performance" (with N.S. Bowen), IEEE Transactions on Computers; vol. 41, pp. 516 – 525; May.'92.
76. "Accelerated Dynamic Learning for Test Pattern Generation in Combinational Circuits" (with W. Kunz), IEEE Transactions on Computer-Aided Design; vol. 12, no. 5, pp. 684 – 694; May.'93.
77. "Survey of Checkpoint and Rollback Recovery Techniques" (with N. Bowen), Computer; vol. 26, no. 2, pp. 22 – 31; Feb.,'93.
78. "Fault-Tolerant Design Strategies for High Reliability and Safety" (with N. Vaidya), IEEE Transactions on Computers; vol. 42, no. 10; Oct.,'93.
79. "A New Class of Bit and Byte Error Control Codes" (with N. Vaidya), IEEE Transactions on Information Theory; pp.1617-1623; Sept.,'92.
80. "Yield Optimization in Large RAMs with Hierarchical Redundancy" (with N. Ganathy and A. D. Singh), IEEE Journal of Solid State; vol. 26, no. 9, pp.1259 – 1264; Sept.,'1.
81. "A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression" (with S.K. Gupta), IEEE Transactions on Computers; vol. 40, no. 6, pp. 743 – 763; June.'91.
82. "Consensus with Dual-Mode Failures" (with F. J. Meyer), IEEE Transactions on Parallel and Distributed Systems; vol. 2, no. 2, pp. 214 – 222; April.'91.
83. "Error Correcting Codes in Fault-Tolerant Computers" (with E. Fujiwara), Computer; vol. 23, no. 7, pp. 63 – 72; July.'90.
84. "Aliasing Probability for a Multiple-Input Signature Analyzer and a New Compression Technique" (with S. Gupta and M. Karpovsky), IEEE Transactions on Computers; vol. 39, pp. 586 – 591; April.'90.
85. "Organization and Analysis of Gracefully-Degrading Inter-leaved Memory Systems" (with K. Saluja, G. Sohi and K. Cheung), IEEE Transactions on Computers; vol. 39, no. 1, pp. 63 – 71; Jan.,'90.

86. "Modeling Defect Spatial Distribution" (with F. J. Meyer), IEEE Transactions on Computers; vol. 38, no. 4, pp. 538 – 546; April.'89.
87. "The DeBruijn Multiprocessor Networks: A Versatile Parallel Processing Network for VLSI" (with M. Samatham), IEEE Transactions on Computers; vol. 38, no. 4, pp. 567 – 581; April.'89.
88. "Dynamic Testing Strategy for Distributed Systems" (with F.J. Meyer), IEEE Transactions on Computers; vol. 38, no. 3, pp. 356 – 365; March.'89.
89. "TRAM: A Design Methodology for High-Performance Testable Large RAMs'' (with N. Jarwala), IEEE Transactions on Computers; vol. C-37, no. 10, pp. 1235 – 1250; Oct.,'88.
90. "Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay" (with I. Koren and Z. Koren), IEEE Journal of Solid State Circuits; vol. 23, pp. 859 – 866; June.'88.
91. "Flip Trees: A Fault-Tolerant Network with Wide Containers" (with F. J. Meyer), IEEE Transactions on Computers; vol. 37, no. 4, pp. 472 – 478; April 1988.
92. "Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems" (with I. Koren), IEEE Transaction on Computers; vol. C-36, no. 3, pp. 344 – 355; April.'87.
93. "Yield and Performance Enhancement through Redundancy in VLSI and WSI Multiprocessor Systems" (with I. Koren), IEEE Proceedings; vol. 74, no. 5, pp. 699 – 711; May.'86.
94. "Dynamically Restructurable Fault-Tolerant Processor Network Architectures", IEEE Transactions on Computers; vol. C-34, no. 5, pp. 434 – 447; May.'85.
95. "Fault-Tolerant Multiprocessor Structures", IEEE Transactions on Computers; vol. C- 34, no. 1, pp. 33 – 45; Jan.,'85.
96. "Synthesis of Directed Multi-Commodity Flow Problems" (with A. Itai), Networks; vol. 14, pp. 213 – 224; '84.
97. "Sequential Network Design Using Extra Inputs for Fault Detection", IEEE Transactions on Computers; vol. C-32, no. 3, pp. 319 – 323; March.'83.
98. "A Fault-Tolerant Distributed Processor Communication Architecture" (with S. Reddy), IEEE Transactions on Computers; vol. C-31, no. 9, pp. 863 – 870; Sept.,'82.
99. "A Class of Unidirectional Error-Correcting Codes", IEEE Transactions on Computers, Special Issue on Fault-Tolerant Computing; vol. C-32, no. 6, pp. 564 – 568; June .'82.

100. "A Uniform Representation of Permutation Networks Used in Memory-Processor Interconnection" (with K. L. Kodandapani), IEEE Transactions on Computers, Special Issue on Parallel Processing; vol. C-29, no. 9, pp. 777 – 791; Sep.,'80.
101. "A New Class of Error Correcting-Detecting Codes for Fault-Tolerant Computer Applications", IEEE Transactions on Computers, Special Issue on Fault-Tolerant Computing; vol. C-29, no. 6, pp. 471 – 481; June.'80.

102. "Error-Correcting Codes and Self-Checking Circuits" (with J.J. Stiffler), IEEE Computer, Special Issue on Fault-Tolerant Computing; vol. 13, no. 3, pp. 27 – 38; March.'80.
103. "Undetectability of Bridging Faults and Validity of Stuck-at Fault Test Sets" (with K.L. Kodandapani), IEEE Transactions on Computers; vol. C-29, no. 1, pp. 55 – 59; Jan.,'80.
104. "Fault-Tolerant Asynchronous Networks Using Read-Only Memories", IEEE Transactions on Computers; vol. C-27, no. 7, pp. 674 – 679; July.'78.
105. "Fault-Secure Asynchronous Networks", IEEE Transactions on Computers; vol. C-27, no. 5, pp. 396 – 404; May.'78.
106. "A Theory of Galois Switching Functions", IEEE Transactions on Computers; vol. C- 27, no. 3, pp. 239 – 249; March '78.
107. "Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays", IEEE Transactions on Computers; vol. C-27, no. 2, pp. 181 – 187; Feb.,'78.
108. "Store-Address Generator with Built-In Fault Detection Capabilities" (with M. Y. Hsiao & A. M. Patel), IEEE Transactions on Computers; vol. C-26, no. 11, pp. 1144 – 1147; Nov.,'77.
109. "A Graph-Structural Approach for the Generalization of Data Management Systems", Information Sciences, American Elesevier Publishing Company, Inc., pp. 1 – 17; March.'77.
110. "Techniques to Construct (2,1) Separating Systems from Linear Codes" (with S.M. Reddy), IEEE Transactions on Computers; vol. C-25, no. 9, pp. 945 – 949; Sept.,'76.
111. "Reed-Muller Canonic Forms for Multivalued Functions" (with A.M. Patel), IEEE Transactions on Computers; vol. C-24, no. 2, pp. 206 – 220; Feb.,'75.
112. "Fault-Tolerant Carry Save Adders", IEEE Transactions on Computers; vol. C-23, no. 11, pp. 1320 – 1322; Nov.,'74.

113. "Design of Two-Level Fault-Tolerant Networks" (with S.M. Reddy), IEEE Transactions on Computers; vol. C-23, no. 1, pp. 41 – 48; June '74.
114. "Fault-Tolerant Asynchronous Networks" (with S.M. Reddy), IEEE Transactions on Computers, Vol. C-22, No. 7, pp. 662-669, July.'73.
115. "Error-Correcting Techniques for Logic Processors" (with S.M. Reddy), IEEE Transactions on Computers; vol. C-21, no. 12, pp. 1331 – 1335; Dec.,'72.

CONFERENCE PROCEEDINGS

1 A Fast and Effective DFT for Test and Diagnosis of Power Switches in SOCs. Design, Automation, and Test in Europe (DATE) Conference (with M. Huang, J. Mathew, R. Shafik, S. Bhattacharjee).

2 "Integrated Software Tools for the memory Management of Low-Energy Embedded Signal Processing Systems", 2012 5th International Congress on Image and Signal Processing (CISP 2012), (with F. Balasa)

3 A Closed-loop Control Strategy for Glucose Control in Artificial Pancreas Systems. In: IEEE Computer Society Intl. Symposium on Electronic Systems Design (Galadanci, J, Shafik, R.A, J. Mathew)

4 "STEP: A Unified Design Methodology for Secure Test and IP Core Protection", in Proceedings of the 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 333--338. (with P. Yeolekar, R. A. Shafik, J. Mathew, and S. P. Mohanty)

5 "RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework", in Proceedings of the 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 189--194, 2012. (with R. A. Shafik, B. M. Al-Hashimi, J. Mathew and S. P. Mohanty,)

6 "The DeSyRe Project: on-Demand System Reliability", in Digital System Design, 2012, Invited Paper, (with I. Sourdis et al)

7 Single-Event Transient Analysis in High Speed Circuits. International Symposium on Electronic System Design (ISED), 2011, pp. 112–117. December 2011 (with J. Mathew, H. Mohammad et al).

8 "Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization", accepted at 24th International Conference on VLSI Design, pp. 304 -309, 2011 (with S. Banerjee, J. Mathew , D. K. Pradhan, S. Mohanty and M. Ciesielski)

9 "BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits", in Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED), 2011. (with Mahesh. P., J. Mathew, A. Jabir),

10 "Multiple bits Error Detection and Correction in GF Arithmetic Circuits", accepted at International Symposium on Electronic System Design (ISED), pp. 101-106, 2010. (with J. Mathew, P. Mahesh, A. M Jabir)

11 "On the Design of Different Concurrent EDC Schemes for S-box and GF(P)", in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 211-218, 2010 (J. Mathew ,S. Mohanty and M. Ciesielski)

12 "Algorithms for Rare Event Analysis in Nano-CMOS Circuits Using Statistical Blockade", in Special Session on New Horizons in SoC and ASIC Design, Proceedings of the International SoC Design Conference (ISOCC), pp. 162--165, 2010 (with Luo Sun. , J. Mathew).

13 "Synthesis of Attack Tolerant Cryptographic Hardware Implementation", In the Proceedings of 18th IEEE/IFIP International Conference on VLSI and System-On-Chip, pp. 286-291, 2010. (with. J. Mathew).

14 "A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization" accepted at International Symposium on Electronic System Design (ISED), pp. 71-76, 2010(with S. Banerjee, J. Mathew , D. K. Pradhan, S. Mohanty and M. Ciesielski)

15 "Fault Diagnosis in Multi Layered De Bruijn Based Architectures for Sensor Networks/", 6^th IEEE Int Workshop on Sensor Networks and Systems for Pervasive computing/ (PerSeNs 2010)/ 2010. (with Anas Abu Taleb. J. Mathew)

16 "Clustered De Bruijn Based Multi Layered Architectures for Sensor Networks", The second International conference on Wireless and Mobile Networks, pp. 123-136, Turkey 2010. (with Anas Abu Taleb. J. Mathew)
17 "Efficient Fault Tolerant De Bruijn Based Design Approach for Sensor Networks", 4^th International Conference on Sensor Technologies and Applications, 2010. SENSORCOMM '10, Italy, July 2010 . (with Anas Abu Taleb. J. Mathew)
18 C-Testable S-box Implementation for Secure Advanced Encryption Standard. IEEE International Online Test Syposium, pp. 210 – 211, IOLTS 2009. (with H Rahaman, J. Mathew).

19 Investigating the Impact of NBTI on Different Power Saving Cache Strategies. in proceedings of IEEE International Conference, DATE, pp. 592 – 597, March 2010, Germany. (with A. Ricketts, J. Singh, V. Narayanan).

20 A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM, in Proceedings of the 23rd IEEE International Conference on VLSI Design (ICVD), pp. 45 – 50, Jan 2010. (with G. Thakral, S. P. Mohanty, D. Ghai)

21 A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead, in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 131-138, 2010. (with J. Singh, D. S. Aswar, and S. P. Mohanty).

22 Layout-Aware Illinois Scan Design for High Fault Coverage, in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 683 – 688, March 2010. (with S. Banerjee, J. Mathew, and S. P. Mohanty).

23 P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP, in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 176-183, 2010. (with G. Thakral, S. P. Mohanty, D. Ghai).

24 On the Design of Different Concurrent EDC Schemes for S-box and GF(P), in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 211-218, 2010. (with J. Mathew, H. Rahaman, A. Jabir, S. P. Mohanty).

25 Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications. To appear in the proceedings of IEEE International Electron Devices Meeting (IEDM), pp. 949 – 951, December, Baltimore, 2009 (with S. Mookerjea, A. Liu, S. Datta, D. Mohata, R. Krishnan, Jawar Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom).

26 A Novel Si-Tunnel FET Based SRAM Design for Ultra Low-Power 0.3V VDD Application. To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), Taipei, Taiwan. pp. 181 -186. Jan 2010. (with J. Singh, K. Ramakrishnan , S. Mookerjea, S. Datta, V. Narayanan).

27 Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems, Design Automation and Test Conference, DATE, pp. 917 – 922. April 2009. (J. Singh, J. Mathew, S. Mohanty).

28 Increasing Memory Yield in Future Technologies through Innovative Design. IEEE International Symposium on Quality Electronic Design. (ISQED 09). pp. 622 – 626, March 2009. (with C.Argyrides, C. Lisboa, A. Al Yamani, Luigi C.)
29 Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms. 1st HiPEAC Workshop on Design for Reliability (DFR'09). January 2009.(with C. Argyrides, C A Lisboa, L. Carro)
30 Analysis of Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems, Design Automation and Test Conference, DATE, pp. 307-312, 2009. (J. Singh, J. Mathew, S. Mohanty).

31 Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems, VLSI Design, pp. 307-312, Jan 2009. (J. Singh, J. Mathew, S. Mohanty).

32 Design Techniques for Bit-Parallel Galois Field Multipliers with Online Single Error Correction and Double Error Detection, IEEE International Online Testing Symposium (IOLTS), pp. 16-21, 2008 (with J. Mathew).

33 Fault Tolerant Reversible Finite Field Arithmetic Circuits, IEEE International Online Testing Symposium (IOLTS), pp. 188-189, 2008 (with J. Mathew, J. Singh" ).

34 Pseudo Parallel Architecture for AES with Error Correction, In: 21th IEEE International System On Chip Conference (IEEE SOCC 2008), pp. 187-190, September 2008 IEEE-SOC 2008 (with J. Mathew).

35 Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations, In: 21th IEEE International System On Chip Conference, IEEE-SOC, pp. 251-254, 2008 (with J. Mathew, S. Mohanty).

36 "A Subthreshold Single Ended I/O SRAM Cell Design for Nanometer CMOS Technologies", In: 20th IEEE International System On Chip Conference (IEEE SOCC 2007), pp. 243-246, September 2008. (J. Singh, J. Mathew, S. Mohanty),

37 "Fault Tolerant Bit Parallel Finite Field Multipliers Using LDPC Codes", ISCAS, pp. 1684 – 1687, May 2008. (with J. Mathew, J. Singh)

38 "A Nano-CMOS Process Variation Induced Read Failure Tolerant SRAM Cell" ISCAS, pp. 3334-3337, 2008. (with, J. Singh, J. Mathew, S. Mohanty).

39 "De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs" Design Automation and Test Conference, DATE, pp. 1370-1373, 2008 (with M. Hosseinabady, M. Reza, J. Mathew).

40 "Single Error Correcting Finite Field Multipliers over GF(2^m), VLSI Design, pp. 33-38, 2008. ( J. Mathew, A Costas, A.M. Jabir).

41 "A Galois Field Based Logic Synthesis Approach with Testability", VLSI Design, pp.629-634, 2008. (with J. Mathew, H. Rahaman, A.M. Jabir).

42 "Design of Reversible Finite Field Arithmetic Circuits with Error Detection", VLSI Design, pp. 453-459, 2008. (with J. Mathew).

43 Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430 (with H. Rahaman, Jimson Mathew, B. K. Sikdar).

44 "Area efficient pseudo parallel Galois field Multiplier", IEEE Norchip Conference, pp. 1-4, 2007( with J. Mathew, H. Rahaman, A. M. Jabir).

45 Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208 (with J. Mathew, H. Rahaman).

46 "Soft-Error induced System-Failure Rate Analysis in an SoC", IEEE Norchip pp. 1-4, Nov 2007(with T. Makkiel, J. Mathew).

47 "Statistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices" IEEE Norchip Conference, pp. 1-4, 2007 (with J. Singh, J. Mathew and D. K. Pradhan).

48 Gfxpress: An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). In:IEEE Transactions on Computer Aided Design, (IEEE TCAD), IEEE, pp. 698-711, April 2008 (with A. Jabir, Dhiraj Pradhan and J. Mathew).

49 "Reliable Network-on-Chip Based on Generalized de Bruijn Graph" In: IEEE International High Level Design Validation and Test Workshop(HLDVT), IEEE, pp. 3-10, November 2007(M. Hosseinabady, M. Reza, J. Mathew).

50 "A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications". In: 20th IEEE International System On Chip Conference (IEEE SOCC 2007), pp. 309-312, September 2007 (B. R. Jose, J Mathew, P. Mythili).

51 "Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories" Proceedings of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Rome, ITALY September 26-28, 2007 (A. Costas, H.R. Zarandi, D.K. Pradhan).

52 "Highly Reliable Power Aware Memory Design" Proceedings of IEEE International On-Line Testing Symposium 2007 (IOLTS), pp. 189-190, Hersonisos of Heraklion, Crete, Greece, July 20-24, 2007 (with Costas Argyrides)

53 "An Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory" Proceedings of European Test Symposium (ETS), Freiburg, Germany, May 20-24, 2007 (with H.R. Zarandi, D.K. Pradhan)

54 "Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs" Proceedings of European Test Symposium (ETS), Freiburg, Germany, May 20-24, 2007 (with H.R. Zarandi, S.G. Miremadi, Costas Argyrides,)

55 "Multiple Upsets Tolerance in SRAM Memory", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 365-368, New Orleans, USA, 27-30 May, 2007. (with Costas Argyrides, H.R. Zarandi)

56 "CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3696-3699, New Orleans, USA, 27-30 May, 2007. (with H.R. Zarandi, S.G. Miremadi, Costas Argyrides)

57 "Non-square Meshes for Improved Yield in Nanotechnology Circuits", Proceedings of IEEE Latin American Test Workshop (LATW), Cuzco, Peru, 11 - 14, March 2007(Costas Argyrides, Ramsundar S, A. Al-Yamani)

58 "Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs " Proceedings of IEEE Latin American Test Workshop (LATW), Cuzco, Peru, 11 - 14, March 2007 (with Costas Argyrides, Demetriou S).

59 "Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs", Proceedings of 14th IEEE Reconfigurable Architecture Workshop, in associated with IPDPS, pp. 1-6, California, USA, 26-27 March, 2007 (H.R. Zarandi, S.G. Miremadi, Costas Argyrides).

60 "Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers over GF(2m)",(with H. Rahaman, J. Mathew) VLSI Design 2007, pp. 479-484, Bangalore, January 2007.

61 "Performance Analysis of an Error Tolerant Low Power Memory Architecture" IEEE International Design and Test Workshop, 19-20 November 2006, Dubai (Costas Argyrides, Jimson Mathew, Ahmad A. Al-Yamani)

62 "An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m)" (with A. M. Jabir, J. Mathew), ICCAD '06; San Jose, CA., pp.151-157, November 5-9, 2006.
63 "Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)", (with H. Rahaman, J. Mathew, A. M. Jabir) IEEE International High Level Design Validation and Test Workshop(HLDVT), California, pp. 48-54, Nov 8-10, 2006 .

64 "Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture" (with J. Mathew, K. Maharatna), IEEE International Conference on Communication Systems, pp. 1-5, Singapore, 2006.

65 "A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks" (with J. Mathew, K. Maharatna), IEEE PRIME Conference, June 2006.
66 Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip.(with C. Liu, Z. Link) In: Design, Automation and Test in Europe Conference and Exhibition, DATE 2006, pp. 303-308, March 2006.

67 "MODD for CF: A Representation for Fast Evaluation of Multiple Output Function", HLDVT, pp. 61-66, Nov, 2004. (with Rajaprabhu T. L., Ashutosh K. Singh, Abusaleh M. Jabir)

68 "Galois Switching Theory: A Uniform Framework for Multi-Level Verification", (with Rajaprabhu T. L., Ashutosh K. Singh, Abusaleh M. Jabir); IEE Proceeding of SoC Design, Test and Technology 2004, September 15, 2004, Loughborough University, Loughborough, UK.

69 "NIVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT Instances", (with S. Subbarayan) Proceedings of The Seventh International Conference on Theory and Applications of Satisfiability Testing (SAT '04), May 2004. pp. 351-356.

70 "Test Scheduling for Network-on-Chip with BIST and Precedence Constraints", International Test Conference, pp. 1369~1378, Oct. 2004.

71 "MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions", (with A. Jabir); Design Automation and Test in Europe, 2004; Paris, France, pp. 1388 – 1389, Feb., '04.

72 "Mathematical Framework for Representing Discrete Functions as Word-Level Polynomials", (with S. Askar & M. Ciesielski); Proc. of Int. High-Level Design Validation and Test in Europe 2004; pp. 135-139.

73 "Logic Transformation and Coding Theory-Based Frameworks for Boolean Satisfiability"; Proc. Of Int. High-Level Design Validation and Test; Nov., '03; pp. 57-62.

74 "EBIST: A Novel Test Geneerator with Built-In Fault Detection Capability; (with Chunsheng Liu and Krish Chakraborty); DATE 03; Munich, Germany; pp. 224-229, March 2003.

75 "Wormhole Routing in DeBruijn Networks and Hyper-DeBruijn Networks", (with E. Ganesan); Invited Paper, ISCAS, pp. 870-873, May 2003.

76 "A Novel Routing Strategy for Ad-Hoc Wireless Local Area Networks", (with N. H. Vaidya and M. Chatterjee), ACM SIGCOMM Computer Communications Review; April, 1997.

77 "Improving Performance of TCP over Wireless Networks" (with B. Bakshi and N. H. Vaidya), Proceedings of IEEE Intl. Conf. on Distributed Computing Systems (ICDCS); pp. 365-373, October 1997.

78 "Verilat: Verification Using Logic Augmentation and Transformations" (with D. Paul and M. Chaterjee), IEEE/ACM Conference on Computer Aided Design, pp. 88 – 95; Los Alamitos, CA.; 1996.

79 "Gate-level Synthesis for Low-Power using New Transformations" (with M. Chatterjee, M. V. Swarna and W. Kunz), 1996 International Symposium on Low Power Electronics and Design, pp.297 – 300; Monterey, CA.; 1996.

80 "Cooperating Diverse Experts: A Methodology to Develop Quality Software for Critical Support Decision Support Systems" (with H. Hecht, M. Hecht and N. Vaidya), 1995 IEEE Aerospace Applications Conference, pp. 49 – 60; Aspen, CO.; 1995.

81 "Recoverable Mobile Environment - Design and Trade-off Analysis" (with P. Krishna and Vaidya, N.), Proc. of the Intl. Conference Symposium on Fault - Tolerant Computing, pp. 16 – 25; Sendai, Japan; June 1996.

82 "Sequential Redundancy Identification using Recursive Learning" (with W. Cao), IEEE/ ACM Intl. Conference on Computer Aided Design, pp. 56 – 62; Los Alamitos, CA.; 1996.

83 "Static and Adaptive Location Management in Mobile Wireless Networks" (with N. H. Vaidya), Journal of Computer Communications (Special Issue on Mobile Computing); vol. 19, no. 4, pp. 321 – 334; April 1996.

84 "Providing Seamless Communication in Mobile Wireless Networks" (with B. Bakshi and N. H. Vaidya), Proceedings of 21st Local Computer Networks (LCN); pp. 535-543, October 1996.

85 "Recovery in Mobile Environments: Design and Trade-off Analysis" (with N. H. Vaidya), Proceedings of 26th Intl. Symposium on Fault Tolerant Computing (FTCS); pp. 16 – 25; June 1996.

86 "Recoverable Mobile Environment: Design and Trade-Off Analysis" (with P. Krishan and N. Vaidya), Proc. Of Intl. Conference on Fault-Tolerant Computing, pp. 16 – 25; Los Alamitos, CA.; 1996.

87 "Efficient Coordinated Checkpointing Scheme for Multicomputers" (with D. Das Sharma), Proc. Of the Conference on Fault-Tolerant Parallel Distributed Systems, pp. 36 – 42; Piscataway, NJ.; 1995.

88 "LOT: Logic Optimization with Testability - New Transformations using Recursive Learning" (with M. Chatterjee and Wolfgang Kunz), ICCAD '95; San Jose, CA. pp. 318-325, November 5-9, 1995.
89 "Performance and Reliability Assessment of I/O Subsystems" (with F. Meyer, and N. Vaidya), 4th IEEE International Workshop on Evaluation Techniques for Dependable Systems; San Antonio, TX.; October 2-3 1995.
90 "Enhance Tool for Evaluating the Dependability of Fault Tolerant Computing System" (with B. Bakshi, J. Yoon, G. Holland, and N. Vaidya), 4th IEEE International Workshop on Evaluation Techniques for Dependable Systems; San Antonio, TX.; October 2-3 1995.
91 "Routing in Mobile Wireless Networks" (with P. Krishna, M. Chatterjee and N. Vaidya), USENIX Symposium on Mobile and Location-Independent Computing; Boston, MA.; April 1995.

92 "A Cluster-Based Approach for Routing in Ad-Hoc Networks" (with P. Krishna, M. Chatterjee and N. Vaidya), USENIS Symposium on Mobile and Location-Independent Computing, pp. 1 – 10; April 1995.
93 "Modified Tree Structure for Location Management in Mobile Environments" (with S. Dolev and J. Welch), IEEE INFOCOM '95, pp. 530-537, Boston, MA.; April 2-6, 1995.
94 "On Improving OBDD-Based Verification in a Synthesis Environment" (with S. Reddy and W. Kunz), 32nd Design Automation Conference; June 1995.
95 "Providing Seamless Communications in Mobile Wireless Networks" (with P. Krishna, B. Bakshi and N. Vaidya), 1st International Conference on Mobile Computers and Networking; pp. 535-543, Berkeley, CA.; November 14-15, 1995.
96 "Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment" (with S. Reddy, and W. Kunz), 32nd Design Automation Conference, pp. 414 – 419; San Francisco, CA. June 12-16, 1995.
97 "Design Methodology for Test Synthesis in BIST" (with M. Chatterjee), IEEE BIST/DFT Workshop; March 1995.

98 "A Novel Pattern Generator for Near Perfect Fault-Coverage" (with M. Chatterjee), IEEE VLSI Test Symposium, pp. 417 – 425; April 1995.
99 "ATPG-Based Transformations for Random-Pattern Testable Logic Synthesis" (with M. Chatterjee and W. Kunz), IEEE/ACM Intl. Conference on CAD; November 1995.

100 "A Cluster-Based Approach for Routing in Ad-Hoc Networks" (with M. Chatterjee and N. H. Vaidya), Proceedings of USENIX Symposium on Location Independent and Mobile Computing; pp. 1-10, April 1995.

101 "Functional Learning: A New Approach to Learning in Digital Circuits" (with Mukherjee and Jain), 12th IEEE VLSI Test Symposium, pp. 122 – 127; Cherry Hill, NJ, April 25-28, 1994.
102 "New Pseudo-Random Test Pattern Generators for Stuck-at and Transition Faults" (with M. Chatterjee), 12th IEEE VLSI Test Symposium; April 26-29, 1994.
103 "Bit-Serial Generalized Median Filters" (with B. Kar), IEEE International Symposium for Computer Aided Systems; pp. 85-88, 1994.
104 "Job Scheduling in Mesh Multicomputers" (with D. Das Sharma), 1994 International Conference on Parallel Processing; vol. II, pp. 251 – 258; 1994.
105 "Subcube Level Time-Sharing in Hypercube Multicomputers" (with D. Das Sharma, and G. Holland), 1994 International Conference on Parallel Processing; Vol. II, pp. 134 – 142; 1994.
106 "GLFSR-A New Test Pattern Generator for BIST" (with M. Chatterjee), 1994 International Test Conference, pp. 481 – 490; 1994.
107 "Location Management in Distributed Mobile Environment" (with P. Krishna and N. Vaidya), Proc. of the 3rd International Conference on Parallel and Distributed Information Systems, pp. 81 – 88; September 1994.
108 "Recovery in Multicomputers with Finite Error Detection Latency" (with P. Krishna and N. Vaidya), Proceedings of International Conference on Parallel Processing, pp. 206 – 210; August 1994.
109 "Location Management in Distributed Mobile Environment" (with N. H. Vaidya), Proc. of 3rd Intl. Conf. on Parallel and Distributed Information Systems; pp. 81-88, Sept., '94.

110 "An Efficient Coordinated Checkpointing Scheme for Multicomputer Applications" (with D. Das Sharma), IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems; pp. 36-42, 1994.

111 "Recovery in Multicomputers with Finite Error-Detection Latency" (with N. H. Vaidya), Proc. of Intl. Conf. on Parallel Processing (ICPP); pp.206-210, August 1994.

112 "Scalability of Binary de Bruijn Graphs", International Symposium of Parallel and Distributed Processors; pp.796-799, 1993.
113 "Binary de Bruijn Networks for Scalability and I/O Processing" (with B. Kar), 5th IEEE Symposium on Parallel Processing; Dallas, TX.; December 1993.
114 "Recovery in Distributed Mobile Environments" (with P. Krishna and N. Vaidya), Proceedings of IEEE Workshop on Advances in Parallel and Distributed Systems, pp. 83 – 88; October 1993.
115 "An Application-Specific Processor for Implementing Stack Filters" (with B. Kar and C.K. Ravikumar), ASAP, pp. 196-199, 1993.
116 "A New Algorithm for Order Statistic and Sorting", IEEE Transactions on Signal Processing; vol. 41, pp. 2688 – 2694; August 1993.
117 "Synthesis of Initializable Asynchronous Circuits" (with S Chakradhar, S. Banerjee and R. Roy), International Conference on VLSI Design; pp. 254-263, Calcutta, India; December 1993.
118 "A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits" (with J. Saxena), 1993 International Conference on Computer-Design, pp. 518 – 522; Cambridge, Massachusetts; October 4-6, 1993.

119 "Design for Testability of Asynchronous Sequential Circuits" (with J. Saxena), International Test Conference; pp. 518-522, Baltimore, MA. October 17-21, 1993.

120 "Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessor" (with D. Das Sharma), 1993 International Conference on Parallel Processing; pp. 118-127, Chicago; August 1993.
121 "A Synthesis and Evaluation Tool for Fault-Tolerant Multiprocessor Architectures" (with J. Clark), Annual Reliability and Maintainability Symposium, pp. 428 – 435; January 1993.
122 "Buffer Assignment for Data Driven Architectures" (with M. Chatterjee), International Conference on Computer Aided Design '93; pp. 665-668, November 1993.
123 "A Fast and Efficient Strategy for Sub-Mesh Allocation in Mesh-Connected Parallel Computers" (with D. Das Sharma), 5th IEEE Symposium on Parallel and Distributed Processing; pp. 682-689, December 1993.
124 "Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks" (with E. Ganesan), International Parallel Processing Symposium; pp. 655-660, April 1993.
125 "Degradable Agreement in the Presence of Byzantine Faults" (with N. Vaidya), 13th Int Conference on Distributed Computing Systems; pp. 237-244, Pittsburgh, PA. May 1993.
126 "Recovery in Distributed Mobile Environments" (with N. H. Vaidya), Proc. of IEEE Workshop on Advances in Parallel and Distributed Systems; pp. 83-88, August 1993.

127 "A Novel Approach for Subcube Allocation in Hypercube Multiprocessor" (with D. Das Sharma), IEEE Symposium on Parallel and Distributed Processing, pp. 336 – 345; Dallas, Texas; 1992.
128 "A Fault-Tolerance Scheme for a System of Duplicated Communicating Processes" (with N. Vaidya), IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems; Amherst, MA. July 1992.

129 "Roll-Forward Checkpoing Scheme: Concurrent Retry with Nondedicated Spares"; (with N. Vaidya), IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems; Amherst, MA; July 1992.
130 "A Design for a Testability Scheme to Reduce Test Application Time in Full Scan'' (with J. Saxena), 10th IEEE VLSI Symposium, pp. 55 – 60; Atlantic City, NJ.; April 1992.
131 "Signature Analysis under a Delay Fault Model'' (with J. Saxena), European Conference on Design Automation, pp. 285 – 290; Brussels, Belgium; March 1992.
132 "A Hierarchical Directory Scheme for Large-Scale Cache Coherent Multiprocessors'' (with Y.C. Maa and D. Thiebaut), 6th International Parallel Processing Symposium, pp. 43 – 46; Beverly Hills, CA.; March 1992.
133 "Yield-Optimization of Redundant Multimegabit RAM's using the Center-Satellite Model'' (with D. Das Sharma), IEEE International Conference on Wafer Scale Integration; pp. 200-209, San Francisco, CA.; January 1992.
134 "A Virtual Memory Translation Mechanism to Support Checkpoint and Rollback Recovery'' (with N.S. Bowen), Supercomputing '91, pp. 890 – 899; November 1991.
135 "Two Economical Directory Schemes for Large-Scale Cache Coherent Multiprocessors'' (with Y.C. Maa and D. Thiebaut), ACM SIGARCH Computer Architecture News, pp. 10–18; September 1991.
136 "Technique for Virtual Memory Architecture to Support Checkpoint and Rollback Recovery'' (with N.S. Bowen), IBM Technical Disclosure Bulletin; vol. 34, pp. 451 –457; September, '91.

137 "High Level Synthesis of Data Driven ASICs'' (with B. Patel), Proc. Fourth Annual IEEE International ASIC Conference & Exhibit --- ASIC'91; P13-3/1-4, Rochester, NY; September 1991.
138 "Program Fault-Tolerance Based on Memory Access Behavior'' (with N. S. Bowen), Proc. Int Symp on Fault Tol Comp, pp. 426 – 433; Montreal, Canada; June 1991.
139 "System-Level Diagnosis: Combining Detection and Location''; (with N. H. Vaidya), Proc. 1991 International Symposium on Fault-Tolerant Computing, pp. 488 – 495; Montreal, Canada; June 1991.
140 "A Methodology for Partial Scan Design" (with S. Nori and J. Swaminathan), Proc. Second European Test Conference, pp. 263 – 271; Munich, Germany; April 1991.
141 "Weight/Space Bounded Error Control'', Proc. 1990 International Conference on Information Theory and Its Applications, pp. 31 – 34; Honolulu, Hawaii; November 1990.
142 "Application-Specific VLSI Architectures Based on De Bruijn Graphs'' IEEE Computer Society Publications, pp. 628 – 640; November 1990.
143 "Modeling of Live Lines and Tree Sharing in Multi-Code Memory Systems'', International Conference on Parallel Processing; vol. I, pp. 326 – 330; August 1990.
144 "Zero Aliasing Compression'', Proc. 1990 International Symposium on Fault-Tolerant Computing, pp. 254 – 263; Newcastle, U.K.; July 1990.

145 "On Implementing Improved Access Control Protocol for Shared Data Systems''; (with A. Mendelson and A.D. Singh), Proc. of 1st Annual IEEE Symposium on Parallel and Distributed Computing, pp. 254 – 263; Dallas, TX.; May 1989.

146 "Yield-Modeling and Optimization of Large Redundant RAMs'' (with A. D. Singh and K. Ganapathy), International Conference on Wafer-Scale Integration, pp. 273 – 287; San Francisco, CA.; January 1989.
147 "RTRAM: Reconfigurable and Testable Multi-Bit RAM Design'', International Test Conference, pp. 263 – 278; Washington, DC; September 1988.
148 "A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability'', International Test Conference, pp. 329 – 340; Washington, DC; September 1988.
149 "An Easily-Testable Architecture for Multimegabit RAMs'' (with N. Jarwala), Proc. of International Test Conference, pp. 750 – 758; Washington DC.; September 1987.
150 "Consensus with Dual Failure Modes'' (with F.J. Meyer), Proc. FTCS-17, pp. 48 – 54; Pittsburgh, PA; July 1987.
151 "Cost-Analysis of On-Chip Error-Control Coding for Fault-Tolerant Dynamic RAMs"; (with N. Jarwala), Proc. FTCS-17, pp. 278 – 283; Pittsburgh, PA; July 1987.

152 "Organization and Analysis of Gracefully-Degrading Interleaved Memory Systems'' (with K. Cheung, G. Sohi, K. Saluja), Proc. 14th International Symposium on Computer Architecture, pp. 224 – 231; Pittsburgh, PA;June 1987.
153 "Wafer-Scale Integration of Multiprocessor Systems" (with I. Koren and Z. Koren), Proc. of HICSS-20 Hawaii International Conference on System Sciences, pp. 13 – 20; January 1987.
154 "Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement" (with Israel Koren), Proc. FTCS-15, pp. 330 – 334; Ann Arbor, MI; June 1985.
155 "Dynamic Testing Strategy for Distributed Systems" (with F.J. Meyer), Proc. FTCS-15, pp. 84 – 90; Ann Arbor, MI; June 1985.
156 "A Versatile Sorting Network" (with M.R. Samatham), Proc. 12th Annual Symposium on Computer Architecture, pp. 360 – 367; June 1985.
157 "Fault-Tolerant Multibus Architectures for Multiprocessors" (with M.L. Schlumberger and Z. Hanquan), Proc. FTCS-14, pp. 400 – 408; Kissimee, FL; June 1984.

158 "A Multiprocessor Network Suitable for Single Chip VLSI Implementation", Proc. 1984 IEEE 11th Annual International Symposium on Computer Architecture, pp. 328 – 337; June 1984.
159 "Fault-Tolerant Network Architectures for Multiprocessors and VLSI-Based Systems", Proc. FTCS-13, pp. 436 – 441; Milan, Italy; June 1983.
160 "On a Class of Multiprocessor Network Architectures'', Proc. of International Conference on Distributed Processing, pp. 302 – 311; Miami, FL; October 1982 (also reprinted in Interconnection Networks for Parallel and Distributed Processing, edited by C. Wu and T. Feng; August 1984).
161 "Testing for Delay Faults in a PLA'' (with K. Son), Proc. International Conference on Circuits and Computers, pp. 346 – 349; September 1982.
162 "Interconnections Topologies for Fault-Tolerant Parallel and Distributed Architectures'', Proc. of 10th International Conference on Parallel Processing, pp. 238 – 242; August 1981.

163 "Fault-Diagnosis of Parallel Processor Interconnection Networks'' (with K.M. Falavara-jani), Proc. Eleventh Annual International Symposium on Fault-Tolerant Computing, pp. 209 – 212; June 1981.
164 "A Fault-Tolerant Communication Architecture for Distributed Systems'', Proc. of Eleventh International Conference on Parallel Processing, pp. 214 – 220; June 1981.
165 "A Solution to Load-Balancing and Fault Recovery in Distributed Systems'' (with K. Matsui), Symposium on Reliability in Distributed Software and Database Systems, pp. 89 – 94; July 1981.

166 "Completely Self-Checking Checkers'' (with K. Son), Digest of 1981 Test Conference, pp. 231 – 237; October 1981.
167 "A Fault-Diagnosis Technique for Closed Flow Networks'', Proc. of 1980 Symposium on Fault-Tolerant Computing, pp. 302 – 304;, Kyoto, Japan; October 1980.
168 "Effect of Undetectable Faults on Testing PLAs'' (with K. Son), Digest of 1980 Test Conference, pp. 359 – 367; November 1980.
169 "An Easily Testable Design of PLAs'' (with K. Son), Cherry Hill Test Conference; Philadelphia, PA; November 1980, (reprinted in IEEE Tutorial on VLSI Testing, edited by Rex Rice, 1981).

170 "A Generalization of Shuffle-Exchange Networks'', Proc. of Fourteenth Annual Conference on Information Sciences and Systems; Princeton, NJ; March 1980.
171 "A Framework for the Study of Permutations and Applications to Memory Processor Interconnection Networks'' (with K. L. Kodandapani), Proc. 1979 International Conference on Parallel Processing, pp. 148 – 158; August 1979.
172 "Shift Registers Designed for On-Line Fault Detection'', Proc. of 1978 International Symposium on Fault-Tolerant Computing, pp. 173 – 178; Toulouse, France; June 1978.
173 "A Synthesis Algorithm of Directed Two-Commodity Networks'', 1978 IEEE International Symposium on Circuits and Systems, pp. 93 – 98; New York, NY; May 1978.

174 "Error-Control Techniques for Array Processors'', 1977 International Symposium on Information and Theory; Ithaca, NY; October 1977.

175 "On Undetectability of Bridging Faults'' (with K.L. Kodandapani), Proceedings of 1977 International Symposium on Fault-Tolerant Computing, p. 192; Los Angeles, CA; June 1977.
176 "Fault-Tolerant Fail-Safe Logic Networks'' (with S.M. Reddy), Proceedings on IEEE Compcon, pp. 363 – 366; March 1977.
177 "Further Results on m-RMC Forms'' (with K.L. Kodandapani), Proceedings of 1976 International Symposium on Multivalued Logic, pp. 88 – 93; Logan, Utah; May 1976.
178 "A Graph-Structural Approach to Data Management Systems'' (with L.C. Chang), Proc. Ninth Hawaii International Conference on System Sciences; Western Periodicals, pp. 254 – 258; January 1976.
179 "Fault-Tolerant Asynchronous Networks Using (2,1)-Type Assignments'', Digest of Fifth International Symposium on Fault-Tolerant Computing; Paris, France; June 1975.
180 "Construction on Error-Correcting Codes with Run-Length Limited Properties'', presented in 1974 International Symposium on Information and Theory; Notre Dame, Indiana; November 1974.
181 "Synthesis of Arithmetic and Logic Processors by using Nonbinary Codes'' (with L.C. Chang), Digest of Papers, Fourth International Symposium on Fault-Tolerant Computting; IEEE Computer Society Publications, pp. 4 – 22; June 1974.
182 "A Multi-Valued Switching Algebra Based on Finite Field," Proc., 1974 International Symposium on Multiple-Valued Logic, IEEE Computer Society Publications; vol. 3, pp. 95 – 113; May 1974.
183 "On Fault Diagnosis of Sequential Machines," Proc., VI Hawaii Conference on System Sciences; Western Periodicals; January 1973.
184 "A Design Technique for Synthesis of Fault-Tolerant Adders," (with S.M. Reddy), Digest of Papers of 1972 International Symposium on Fault-Tolerant Computing; IEEE Computer Society Publications, pp. 20 – 25; June 1972.

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